ARuss12
New Contributor
6 years agoModelsim 10.1d and UNDEFINED entities internal signals
Good morning all, This is my first post in this forum, so i apologize in advance if the section is not completely correct. I started recently wih FPGA design, and i am doing some homeworks from my ...
- 6 years ago
Hi,
Thanks for the project file.
Please initialize the all the I/os in test bench like below, then Add the internal signals like 'FF1' & 'FF2' in wave window & try to 'run simulation'.
please find the attachment for screenshot.
SIGNAL STOP : STD_LOGIC := '0'; SIGNAL EnDig1 : STD_LOGIC:= '0'; SIGNAL EnDig3 : STD_LOGIC:= '0'; SIGNAL START : STD_LOGIC:= '0'; SIGNAL LED : STD_LOGIC:= '0'; SIGNAL EnDig0 : STD_LOGIC:= '0'; SIGNAL Digits : STD_LOGIC_VECTOR(6 DOWNTO 0):= "0000000"; SIGNAL EnDig2 : STD_LOGIC := '0'; SIGNAL CLK : STD_LOGIC:= '0';Regards,
Vicky