Modelsim - VHDL common question.

This is my code:

--- Quote Start ---

LIBRARY IEEE;

USE IEEE.std_logic_1164.all;

LIBRARY lpm;

USE lpm.LPM_COMPONENTS.ALL;

USE IEEE.std_logic_arith.all;

USE IEEE.std_logic_signed.all;

ENTITY Ram_Rom IS

PORT(clk: in std_logic;

inaddress : in std_logic_vector(7 downto 0);

data : out std_logic_vector(7 downto 0));

end Ram_Rom;

ARCHITECTURE new_array_arch OF Ram_Rom IS

signal data1 : STD_LOGIC_vector(7 downto 0);

begin

u1: lpm_rom

GENERIC MAP(lpm_width=> 8, lpm_widthad=> 8, lpm_file=> "array.mif",

lpm_address_control=> "registered", lpm_outdata=> "unregistered")

PORT MAP(ADDRESS => inaddress, inclock=> clk, q => data1);

Process(clk)

begin

if clk'event and clk='1' then

data <= data1;

end if;

end process;

end new_array_arch;

--- Quote End ---

When I compile it by Quartus. I saw no logic gate. But when I simulate it in waveforms it still right. Can you explain this for me? Thanks