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Altera_Forum's avatar
Altera_Forum
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15 years ago

Modelsim - VHDL common question.

Dear all my friend I make this thread to post the question related to Modelsim and VHDL I hope everybody can help me answer. Thank you very much. Best regards.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Looks like you're clipping the values somewhere, and or slicing the wrong bits when taking the output from multipliers.

You'll have to take a look in your VHDL to try and find it.

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Thank Tricky

I had already change my code.

For example

mulr(30 downto 15);

mulr(15 downto 0);

...

But it still have the same wanning. I don't know why.

I had already attached my difference equation after Q15 format in this message. Could you check it for me?