Honored Contributor
Honored ContributorI implement the continuous transfer function of the second order low pass filter by VHDL. I don't know why my result are very strange. And I saw a lot of warning when I compile it. Do this wanning affect to my result?
This is warning: --- Quote Start --- Warning (14130): Reduced register "Yn[0]~reg0" with stuck data_in port to stuck value GND Warning (14130): Reduced register "Yn[1]~reg0" with stuck data_in port to stuck value GND Warning (14130): Reduced register "Y1[0]" with stuck data_in port to stuck value GND Warning (14130): Reduced register "Y1[1]" with stuck data_in port to stuck value GND Warning (14130): Reduced register "Y2[0]" with stuck data_in port to stuck value GND Warning (14130): Reduced register "Y2[1]" with stuck data_in port to stuck value GND Warning (14130): Reduced register "Y3[0]" with stuck data_in port to stuck value GND Warning (14130): Reduced register "Y3[1]" with stuck data_in port to stuck value GND Warning (14130): Reduced register "Y4[0]" with stuck data_in port to stuck value GND Warning (14130): Reduced register "Y4[1]" with stuck data_in port to stuck value GND Warning: Output pins are stuck at VCC or GND Warning (13410): Pin "Yn[0]" stuck at GND Warning (13410): Pin "Yn[1]" stuck at GND Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'. Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'. Warning: Found 16 output pins without output pin load capacitance assignment Info: Pin "Yn[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Yn[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Yn[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Yn[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Yn[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Yn[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Yn[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Yn[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Yn[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Yn[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Yn[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Yn[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Yn[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Yn[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Yn[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Yn[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results Info: Pin Yn[0] has GND driving its datain port Info: Pin Yn[1] has GND driving its datain port Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Warning: Found pins functioning as undefined clocks and/or memory enables Info: Assuming node "CLK" is an undefined clock Info: Assuming node "CLK_40n" is an undefined clock --- Quote End --- How to reject this wanning? And this is my code:
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;
LIBRARY lpm;
USE lpm.LPM_COMPONENTS.ALL;
ENTITY STEP IS
port(CLK, CLK_40n :IN STD_LOGIC:='0';
X0 :IN STD_LOGIC_VECTOR(15 downto 0):=(OTHERS =>'0');
Yn :BUFFER STD_LOGIC_VECTOR(15 downto 0):=(OTHERS =>'0'));
END STEP;
ARCHITECTURE STEP_arch OF STEP IS
SIGNAL A0,A1,A2,A3,A4 :STD_LOGIC_VECTOR(15 downto 0):=(OTHERS =>'0');
SIGNAL B1,B2,B3,B4 :STD_LOGIC_VECTOR(15 downto 0):=(OTHERS =>'0');
SIGNAL Y4,Y3,Y2,Y1 :STD_LOGIC_VECTOR(15 downto 0):=(OTHERS =>'0');
SIGNAL X1,X2,X3,X4 :STD_LOGIC_VECTOR(15 downto 0):=(OTHERS =>'0');
SIGNAL mula,mulb :STD_LOGIC_VECTOR(15 downto 0):=(OTHERS =>'0');
SIGNAL mulr :STD_LOGIC_VECTOR(31 downto 0):=(OTHERS =>'0');
SIGNAL adda,addb,addr :STD_LOGIC_VECTOR(15 downto 0):=(OTHERS =>'0');
SIGNAL CNT :STD_LOGIC_VECTOR(4 downto 0):=(OTHERS =>'0');
BEGIN
mull: lpm_mult
generic map(LPM_WIDTHA=>16,LPM_WIDTHB=>16,LPM_WIDTHS=>16,LPM_WIDTHP=>32,
LPM_REPRESENTATION=>"SIGNED",LPM_PIPELINE=>1)
port map(dataa=> mula,datab=> mulb,clock=> clk,result=> mulr);
adder1: lpm_add_sub
generic map(lpm_width=>16,LPM_REPRESENTATION=>"SIGNED",lpm_pipeline=>1)
port map(dataa=>adda,datab=>addb,clock=> clk,result=>addr);
--Q15
A0 <= "0000000000000011";--3
A1 <= "0000000000001011";--11
A2 <= "0000000000010001";--17
A3 <= "0000000000001011";--11
A4 <= "0000000000000011";--3
B1 <= "0101110100111111";--23871
B2 <= "1001101000010100";--- -26092
B3 <= "0011000101011101";---12637
B4 <= "1111011011111100";--- -2308
GEN:block
BEGIN
PROCESS(CLK_40n)
BEGIN
IF CLK_40n'EVENT and CLK_40n='1' THEN
CNT <=CNT+1;
IF CNT="00000" THEN
mula <= A0;
mulb <= X0;
ELSIF CNT="00001" THEN
adda <= mulr(30 downto 15);
mula <= A1;
mulb <= X1;
ELSIF CNT="00010" THEN
addb <= mulr(30 downto 15);
mula <= A2;
mulb <= X2;
ELSIF CNT="00011" THEN
adda <= addr;
addb <= mulr(30 downto 15);
mula <= A3;
mulb <= X3;
ELSIF CNT="00100" THEN
adda <= addr;
addb <= mulr(30 downto 15);
mula <= A4;
mulb <= X4;
ELSIF CNT="00101" THEN
adda <= addr;
addb <= mulr(30 downto 15);
mula <= B1;
mulb <= Y1;
ELSIF CNT="00110" THEN
adda <= addr;
addb <= mulr(30 downto 15);
mula <= B2;
mulb <= Y2;
ELSIF CNT="00111" THEN
adda <= addr;
addb <= mulr(30 downto 15);
mula <= B3;
mulb <= Y3;
ELSIF CNT="01000" THEN
adda <= addr;
addb <= mulr(30 downto 15);
mula <= B4;
mulb <= Y4;
ELSIF CNT="01001" THEN
adda <= addr;
addb <= mulr(30 downto 15);
ELSIF CNT="01010" THEN
Yn <= (addr(15) & addr(12 downto 0) & "00");
ELSIF CNT="01011" THEN
Y1 <= Yn;
Y2 <= Y1;
Y3 <= Y2;
Y4 <= Y3;
X4 <= X3;
X3 <= X2;
X2 <= X1;
X1 <= X0;
CNT <= "00000";
END IF;
END IF;
END PROCESS;
END BLOCK GEN;
END STEP_arch; 