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Altera_Forum
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15 years ago

Modelsim - VHDL common question.

Dear all my friend I make this thread to post the question related to Modelsim and VHDL I hope everybody can help me answer. Thank you very much. Best regards.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

It seems that modelsim does not like x string, so change all these strings to

numerical values (dec or hex) e.g.

A0 <= std_logic_vector(to_signed(3,16));

or A0 <= std_logic_vector(to_signed(16#0003#,16));

I think thats all left