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Altera_Forum
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15 years ago

Modelsim - VHDL common question.

Dear all my friend I make this thread to post the question related to Modelsim and VHDL I hope everybody can help me answer. Thank you very much. Best regards.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi Kaz

It's still error.

I replaced signed and arith with numeric_std.

CNT :Unsigned(7 downto 0);

change

A0 <= x"0003"; to A0 <= 16#0003#;

and try with A0 <= 16' 0003;

or A0 <= 16'h 0003; (like as verilog)

It's still error.