Modelsim - VHDL common question.

I'm sorry.

** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(21): Type error in bit string literal. Type std_logic_vector is not an array of bit.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(22): Type error in bit string literal. Type std_logic_vector is not an array of bit.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(23): Type error in bit string literal. Type std_logic_vector is not an array of bit.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(24): Type error in bit string literal. Type std_logic_vector is not an array of bit.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(25): Type error in bit string literal. Type std_logic_vector is not an array of bit.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(26): Type error in bit string literal. Type std_logic_vector is not an array of bit.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(27): Type error in bit string literal. Type std_logic_vector is not an array of bit.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(28): Type error in bit string literal. Type std_logic_vector is not an array of bit.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(29): Type error in bit string literal. Type std_logic_vector is not an array of bit.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(37): No feasible entries for infix op: "="
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(37): Type error resolving infix expression.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(41): No feasible entries for infix op: "="
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(41): Type error resolving infix expression.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(45): No feasible entries for infix op: "="
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(45): Type error resolving infix expression.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(49): No feasible entries for infix op: "="
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(49): Type error resolving infix expression.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(54): No feasible entries for infix op: "="
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(54): Type error resolving infix expression.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(59): No feasible entries for infix op: "="
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(59): Type error resolving infix expression.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(65): No feasible entries for infix op: "="
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(65): Type error resolving infix expression.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(70): No feasible entries for infix op: "="
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(70): Type error resolving infix expression.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(75): No feasible entries for infix op: "="
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(75): Type error resolving infix expression.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(81): No feasible entries for infix op: "="
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(81): Type error resolving infix expression.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(85): No feasible entries for infix op: "="
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(85): Type error resolving infix expression.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(87): No feasible entries for infix op: "="
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(87): Type error resolving infix expression.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(96): Type error in bit string literal. Type std_logic_vector is not an array of bit.
** Error: D:/Quartus_code/ExModelSim/HW2/step.vhd(101): VHDL Compiler exiting

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;
USE IEEE.numeric_std.all;
ENTITY STEP IS
port(CLK, CLK_40n  :IN  STD_LOGIC;
	X0	:IN STD_LOGIC_VECTOR(15 downto 0);
	Yn	:BUFFER STD_LOGIC_VECTOR(15 downto 0));
END STEP;
ARCHITECTURE STEP_arch OF STEP IS
SIGNAL A0,A1,A2,A3,A4	:STD_LOGIC_VECTOR(15 downto 0);
SIGNAL B1,B2,B3,B4		:STD_LOGIC_VECTOR(15 downto 0);
SIGNAL Y4,Y3,Y2,Y1		:STD_LOGIC_VECTOR(15 downto 0);
SIGNAL X1,X2,X3,X4		:STD_LOGIC_VECTOR(15 downto 0);
SIGNAL mula,mulb		:STD_LOGIC_VECTOR(15 downto 0);
SIGNAL mulr				:STD_LOGIC_VECTOR(31 downto 0);
SIGNAL adda,addb,addr	:STD_LOGIC_VECTOR(31 downto 0);
SIGNAL CNT				:STD_LOGIC_VECTOR(7 downto 0);
BEGIN
A0  <= x"0003";--3      
A1  <=  x"000B";--11      
A2  <=  x"0011";--17    
A3  <=  x"000B";--11
A4  <=   x"0003";--3  
B1  <=  x"5D3F";--23871   
B2  <=  x"9A14";--- -26092
B3  <=  x"3181";---12637
B4  <=  x"F6FF";--- -2305
 
GEN:block
BEGIN
PROCESS(CLK_40n)
BEGIN
IF CLK_40n'EVENT and CLK_40n='1' THEN
	CNT <=CNT+1;
IF CNT=x"00" THEN
	mula <=  A0;
	mulb <=  X0;
	
ELSIF CNT=x"01" THEN
	adda <=  mula*mulb;
	mula <=  A1;
	mulb <=  X1;
ELSIF CNT=x"02" THEN
	addb <=  mula*mulb;
	mula <=  A2;
	mulb <=  X2;
ELSIF CNT=x"03" THEN
	adda <=  adda+addb;
	addb <=  mula*mulb;
	mula <=  A3;
	mulb <=  X3;
ELSIF CNT=x"04" THEN
	adda <=   adda+addb;
	addb <=   mula*mulb;
	mula <=   A4;
	mulb <=   X4;	
ELSIF CNT=x"05" THEN
	adda <=   adda+addb;
	addb <=  mula*mulb;
	mula <=  B1;
	mulb <=  Y1;
ELSIF CNT=x"06" THEN
	adda <=  adda+addb;
	addb <=  mula*mulb;
	mula <=  B2;
	mulb <=  Y2;
ELSIF CNT=x"07" THEN
	adda <=   adda+addb;
	addb <=   mula*mulb;
	mula <=   B3;
	mulb <=   Y3;	
ELSIF CNT=x"08" THEN
	adda <=   adda+addb;
	addb <=  mula*mulb;
	mula <=  B4;
	mulb <=  Y4;
ELSIF CNT=x"09" THEN
	adda <=  adda+addb;
	addb <=  mula*mulb;
ELSIF CNT=x"0A" THEN
	Yn <=   adda(15 downto 0)+addb(15 downto 0);
ELSIF CNT=x"0B" THEN
	Y1       <=  Yn;
	Y2       <=  Y1;
	Y3       <=  Y2;
	Y4       <=  Y3;
	X4       <=  X3;
	X3       <=  X2;
	X2       <=  X1;
	X1       <=  X0;
	CNT     <=  x"00";
END IF;
END IF;
END PROCESS;
END BLOCK GEN;
END STEP_arch;