Modelsim - VHDL common question.

Thank you very much for you help. I had changed all Xs to x. But it still error.

A0  <= x"0003";--3      
A1  <=  x"000B";--11      
A2  <=  x"0011";--17    
A3  <=  x"000B";--11
A4  <=   x"0003";--3  
B1  <=  x"5D3F";--23871   
B2  <=  x"9A14";--- -26092
B3  <=  x"3181";---12637
B4  <=  x"F6FF";--- -2305
 
GEN:block
BEGIN
PROCESS(CLK_40n)
BEGIN
IF CLK_40n'EVENT and CLK_40n='1' THEN
	CNT <=CNT+1;
IF CNT=x"00" THEN
	mula <=  A0;
	mulb <=  X0;
	
ELSIF CNT=x"01" THEN
	adda <=  mula*mulb;--mulr(30 downto 15);
	mula <=  A1;
	mulb <=  X1;
ELSIF CNT=x"02" THEN
	addb <=  mula*mulb;--mulr(30 downto 15);
	mula <=  A2;
	mulb <=  X2;
ELSIF CNT=x"03" THEN
	adda <=  adda+addb;--addr;
	addb <=  mula*mulb;--mulr(30 downto 15);
	mula <=  A3;
	mulb <=  X3;
ELSIF CNT=x"04" THEN
	adda <=   adda+addb;--addr;
	addb <=   mula*mulb;--mulr(30 downto 15);
	mula <=   A4;
	mulb <=   X4;	
ELSIF CNT=x"05" THEN
	adda <=   adda+addb;--addr;
	addb <=  mula*mulb;--mulr(30 downto 15);
	mula <=  B1;
	mulb <=  Y1;
ELSIF CNT=x"06" THEN
	adda <=  adda+addb;--addr;
	addb <=  mula*mulb;--mulr(30 downto 15);
	mula <=  B2;
	mulb <=  Y2;
ELSIF CNT=x"07" THEN
	adda <=   adda+addb;--addr;
	addb <=   mula*mulb;--mulr(30 downto 15);
	mula <=   B3;
	mulb <=   Y3;	
ELSIF CNT=x"08" THEN
	adda <=   adda+addb;--addr;
	addb <=  mula*mulb;--mulr(30 downto 15);
	mula <=  B4;
	mulb <=  Y4;
ELSIF CNT=x"09" THEN
	adda <=  adda+addb;--addr;
	addb <=  mula*mulb;--mulr(30 downto 15);
ELSIF CNT=x"0A" THEN
	Yn <=   adda(15 downto 0)+addb(15 downto 0);--(addr(15) & addr(12 downto 0) & "00");
ELSIF CNT=x"0B" THEN
	Y1       <=  Yn;
	Y2       <=  Y1;
	Y3       <=  Y2;
	Y4       <=  Y3;
	X4       <=  X3;
	X3       <=  X2;
	X2       <=  X1;
	X1       <=  X0;
	CNT     <=  X"00";
END IF;
END IF;
END PROCESS;
END BLOCK GEN;
END STEP_arch;