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Altera_Forum
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15 years ago

Modelsim - VHDL common question.

Dear all my friend I make this thread to post the question related to Modelsim and VHDL I hope everybody can help me answer. Thank you very much. Best regards.
Altera_Forum's avatar
Altera_Forum
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15 years ago

I have a declare hex number in VHDL. When I run it in Quartus, it say error "Type error in bit string literal. Type std_logic_vector is not an array of bit." How to declare hexadecimal in Modelsim?

This is my declare: 


A0  <=   X"0003";--3      
A1  <=  X"000B";--11      
A2  <=  X"0011";--17    
A3  <=  X"000B";--11
A4  <=   X"0003";--3  
B1  <=  X"5D3F";--23871   
B2  <=  X"9A14";--- -26092
B3  <=  X"3181";---12637
B4  <=  X"F6FF";--- -2305

I use Modelsim plus Se 5.7d