Modelsim - Gate Level Simulation works, RTL does not (a second .vo is missing)

Hello,

I have been working on a design that used to have a normal clock signal as an input and I never had any problem to simulate my design. I recently started using a differential clock instead by means of a MegaWizard Altera GPIO Lite module. The problem is that now I cannot run the RTL simulation on Modelsim anymore because I get the following error:

# ** error: (vlog-7) failed to open design unit file ".../project_folder/diff_clk.vo" in read mode.

My top module is called "deserializer" and I do have a "deserializer.vo" file in that folder and I wonder why Modelsim is asking for that file instead, which does not exist because DIFF_CLK is not the top-level entity. Is it taking somehow that module as the top-level entity even though "deserializer" is set on Quartus as my top-level entity and the test bench is defined to simulate the "deserializer" module?

On the other hand, the Gate Level Simulation still works as it used to do when I had a normal clock signal.

Does anyone know what's going on? Thanks in advance.

Regards,

Javiwolf