Forum Discussion
Altera_Forum
Honored Contributor
14 years agoWARNING:
Even though the latest release of Modelsim could be better, its not always compatible with the Quartus simulation IP. I had a case where the altsyncram RAM simulation model provided with Quartus only worked correctly with the version of Modelsim that shipped with that version of Quartus. Here's my notes from the testbench I submitted as part of the SR:
--
-- 1. This testbench works fine when run from Modelsim ALTERA 6.1g
-- (ships with Quartus 7.2 and 8.0)
--
-- However, with Modelsim SE 6.3f, it fails. Writes to the RAM
-- show valid output data after the 2 clock pipeline, but then
-- the data goes to unknown state - even if the address does
-- not change. Byte-enables were asserted during reads, and it
-- made no difference.
The 'solution' was to use only a compatible version of Modelsim. (I never have looked at the difference between altsyncram components to see if the code was actually changed ...). Cheers, Dave