Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHi Dave,
It was ModelSIm choking on the std_logic_2D as well, I didn't try compiling the array_of_slv with Modelsim as I was using Gate Level simulation anyway and using the QII generated testbench with the 'funny' types. Anyway I just worked my way around the one project by making a test-project and generate some data in there to drive the dut and then ran the internal simulator. After that I finished the 'real' project (combining this and another subproject plus a bunch of M4K) under Modelsim, again using Gate Level simulation. I noticed that the Altera Modelsim version is only 6.6d where Mentor have 10.0c out. Maybe that version has decent VHDL 2008 support? But then we would have to spend some additional money. I'll have to find the time to study your 'script' setup more closely, but I have to find a solution/workaround for my 'legacy' std_logic_2D code as well. Thanks for all the support, Josy