Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHi Josy,
--- Quote Start --- Actually I tried a small project to see how the Test Bench Writer (11.0sp1) would handle the unconstrained std_logic_vector. I attach a .qar. I included the std_logic_2D version in the .qar for reference. --- Quote End --- Ok, I see a project and source, but no simulation script. How do you go about simulating this design in Modelsim? I typically use a sim.tcl script to build all the components and create Tcl procedures for the testbench, eg., I just posted a simple example in this thread: http://www.alteraforum.com/forum/showthread.php?t=32386 But I want to know what you are doing, so I can reproduce the error you see. Cheers, Dave