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The problem with the mod or rem operators when they are not 2**N, is that it implements a divider. These have terrible timing performance in a single clock cycle (about 20MHz if you're lucky). So the fact that you're using a 167MHz clock probably meant it was basically producing random values. Do you have timing constraints for the design? did you look at them and see the failures?
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Tricky, thank you. I guess you're right. I haven't learned the timing analysis part of the design yet. I added the following *.sdc file to my project:
create_clock -name clock_50 -period 20
derive_pll_clocks
derive_clock_uncertainty
And here's the "red" TimeQuest report I get with the mod operation:
https://docs.google.com/spreadsheets/d/1pumvhheg8nyqjznpagodadgxgcndvcolb7laxp3bmym/pubhtml I don't know how to interpret this yet but I guess that's you're talking about. Would you please briefly explain what this report say?
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