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Altera_Forum
Honored Contributor
Honored Contributormod operation synthesis (Avalon-MM master writing to DRAM problem)
Hi. I'm trying to write a simple Avalon-MM master component which writes an image to the DRAM memory. I use this component in a Qsys system with Nios II/e processor, SDRAM controller and University P...
Altera_ForumHonored Contributor
Honored ContributorThe problem with the mod or rem operators when they are not 2**N, is that it implements a divider. These have terrible timing performance in a single clock cycle (about 20MHz if you're lucky). So the fact that you're using a 167MHz clock probably meant it was basically producing random values. Do you have timing constraints for the design? did you look at them and see the failures?
