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david_'s avatar
david_
Icon for New Contributor rankNew Contributor
7 years ago
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Mixed language ModelSim/Questa simulations with altera_mf

Hi I have a mixed language design using SystemVerilog, Verilog and VHDL. In this design there are a number of Intel FPGA components, which are either VHDL or Verilog. I am having an issue when tryi...
  • Abe's avatar
    Abe
    7 years ago

    If you're using the Intel Edition ModelSim software, you need not compile the FPGA device libraries again. All you need to do is to include them in the vsim command using the -L <lib_name> .

    altera_mf for VHDL

    and altera_mf_ver for Verilog

    For ex,

    vsim -work ... -L altera_mf_ver include any other device specific libraries this way. On the safer side you could add both VHDL as well as Verilog libraries to the simulation using the -L altera_mf -L altera_mf_ver ... options and try.

david_'s avatar
david_
Icon for New Contributor rankNew Contributor
7 years ago

Hi Abe,

Great thank you for the help, I have followed your advice and it is working now. I am not using Intel Edition, so used the following code:

vlog -work altera_mf_ver $(QUARTUS_HOME)/eda/sim_lib/altera_mf.v
 
vlib altera_mf
vmap altera_mf altera_mf
vcom -work altera_mf -2008 -explicit "$(QUARTUS_HOME)/eda/sim_lib/altera_mf_components.vhd"
vcom -work altera_mf -2008 -explicit "$(QUARTUS_HOME)/eda/sim_lib/altera_mf.vhd"
 
vsim -L altera_mf_ver -64 -voptargs="+acc" -lib ${library} ${top_level} +UVM_TESTNAME=${test_case} +UVM_VERBOSITY=${uvm_verbosity} -do "do wave.tcl; run -all"

David