Mixed blocking and non- with always@ ?

Verilog is defined as a language with bahavioural features. Things work as specified in the LRM when the verilog language is simulated.

Synthesizers (compared to compilers) take the Verilog and convert it to gates and registers - and they will usually specify the templates they accept for various hardware elements in their documentation (Quartus does). This means that not all of the Verilog language is acceptable to a synthesisor. But it is not Verilog LRM job to specify how synthesisors work.

I think you are probably coming at this from the wrong end. There will always be far more verilog features that synthsis tools will never accept - Verilog is also meant to be a modelling language, able to model hardware at an abstracted level.

As a rule of thumb - only use non-blocking assignments inside always blocks, until you understand the consequences of using blocking.# n delays will never be synthesisable (as no circuit exists to allow a specific time period delay to a signal)