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Altera_Forum's avatar
Altera_Forum
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10 years ago

Missing clock assignment warning

Hello, in a Cylone V SOC project under Quartus 14.0 I get the following message from the Linker: Warning (332060): Node: clk50a was determined to be a clock but was found without an associate...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Try:

create_clock -name {clk50a} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk50a}]

Otherwise you create a clock named clk50a to be used for timing analysis, but you don't bind it to any physical signal.

To be clearer, in general you define

create_clock -name {myclk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk50a}]

and then use myclk to analyze this clock net.