Missing Address in input node finder

Hi guys.

I have problem with my coding now. I have design my vhdl code for ROM. The problem is when I want to see the waveform, the input port for "Address" cannot be find in node finder. Could somebody help me? Is it because many address in my ROM? Is there any limitation for address in ROM? Here is my coding.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity ROMSM1 is

port(Clock : in std_logic;

Read : in std_logic;

Address : in std_logic_vector(1 downto 33);

Data_out: out std_logic_vector(7 downto 0));

end ROMSM1;

architecture BehavROMSM1 of ROMSM1 is

type ROM_Array is array (0 to 66)of std_logic_vector(7 downto 0);

constant Content: ROM_Array := (

0 => "10000000", -- value in ROM at location 0H

1 => "10000000", -- value in ROM at location 1H

2 => "10000000", -- value in ROM at location 2H

3 => "00000000", -- value in ROM at location 3H

4 => "00000000",

5 => "00000000",

6 => "00000000",

7 => "00000000",

8 => "00000000",

9 => "00000000",

10 => "00000000",

11 => "00000000",

12 => "00000000",

13 => "00000000",

14 => "00000000",

15 => "00000000",

16 => "00000000",

17 => "00000000",

18 => "00000000",

19 => "00000000",

20 => "00000000",

21 => "00000000",

22 => "00000000",

23 => "00000000",

24 => "00000000",

25 => "00000000",

26 => "00000000",

27 => "00000000",

28 => "00000000",

29 => "00000000",

30 => "00000000",

31 => "00000000",

32 => "00000000",

33 => "00000000",

34 => "00000000",

35 => "00000000",

36 => "00000000",

37 => "00000000",

38 => "00000000",

39 => "00000000",

40 => "00000000",

41 => "00000000",

42 => "00000000",

43 => "00000000",

44 => "00000000",

45 => "00000000",

46 => "00000000",

47 => "00000000",

48 => "00000000",

49 => "00000000",

50 => "00000000",

51 => "00000000",

52 => "00000000",

53 => "00000000",

54 => "00000000",

55 => "00000000",

56 => "00000000",

57 => "00000000",

58 => "00000000",

59 => "00000000",

60 => "00000000",

61 => "00000000",

62 => "00000000",

63 => "00000000",

64 => "10000000",

65 => "10000000",

66 => "10000000",

OTHERS => "11111111");

begin

process(Clock)--, Read, Address)

begin

if( Clock'event and Clock = '0' ) then

if( Read = '1' ) then

Data_out <= Content(conv_integer(Address));

else

Data_out <= "ZZZZZZZZ";

end if;

end if;

end process;

end BehavROMSM1;