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Altera_Forum's avatar
Altera_Forum
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17 years ago

Mismatched Nodes

I am designing a 4 bit ripple adder using input and output buses. They are named A[3..0],B[3..0] and Sum[3..0]. When I try to simulate the circuit though I get these errors: Warning: Wrong node ty...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

After you click simulate button, you will face above errors, then open the Simulation Report window (in this case it will be automatically opened). You will see there are nodes only with width 1, in those nodes go to properties and change the bus width to 4 in your case. I should say this bus width should be adjusted in the simulation report window, not in the *.vwf window.