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Hi,
I look into your project and found that you have specified your input signal A and B with the width of 1. You can change the setting by opening your .vwf, select e.g input A, right
mouse click , properties and change bus width to 4. This should solve your probem.
Kind regards
GPK
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Hi,
What a kind man you are!
My project have the same question,Can you help me?
Thank you
below is my vhdl source file:
library ieee;
use ieee.std_logic_1164.all;
entity yinliaoji is
port(
A: in std_logic;
B: in std_logic;
Y: out std_logic;
Z: out std_logic;
Q: buffer std_logic_vector(1 downto 0)
);
end yinliaoji;
architecture behave of yinliaoji is
begin
process(A,B,Q)
begin
if Q="00" and A='0' and B='0'then Q<="00";Y<='0';Z<='0';
elsif Q="00" and A='0' and B='1'then Q<="01";Y<='0';Z<='0';
elsif Q="00" and A='1' and B='0'then Q<="10";Y<='0';Z<='0';
elsif Q="01" and A='0' and B='0'then Q<="01";Y<='0';Z<='0';
elsif Q="01" and A='0' and B='1' then Q<="10";Y<='0';Z<='0';
elsif Q="01" and A='1' and B='0' then Q<="00";Y<='1';Z<='0';
elsif Q="10" and A='0' and B='0' then Q<="10";Y<='0';Z<='0';
elsif Q="10" and A='0' and B='1' then Q<="00";Y<='1';Z<='0';
elsif Q="00" and A='1' and B='0' then Q<="00";Y<='1';Z<='1';
end if;
end process;
end behave;
Honored Contributor
