Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Mismatched Nodes

I am designing a 4 bit ripple adder using input and output buses. They are named A[3..0],B[3..0] and Sum[3..0]. When I try to simulate the circuit though I get these errors: Warning: Wrong node ty...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

--- Quote Start ---

I didn't know that this forum let you add attachments. So I've attached the zip file to this post.

Thanks :)

--- Quote End ---

Hi,

I look into your project and found that you have specified your input signal A and B with the width of 1. You can change the setting by opening your .vwf, select e.g input A, right

mouse click , properties and change bus width to 4. This should solve your probem.

Kind regards

GPK