Minuimum Pulse Width timing violation with Cyclone IV internal oscillator

A quick follow up, I seem to have solved my own problem, though quite by accident...

I wanted to make the internal clock easier to find when using SignalTap etc. The output of the alt_int_osc megafunction was mapped to a signal int_clk in the top level of my code, so I added a synthesis directive

    attribute keep : boolean;
    attribute keep of int_clk : signal is true;

then changed the entry in my .sdc to reference this node

# Internal RC oscillator, 80 MHz max
create_clock -name "IntClk" -period 12.5ns {int_clk}

The design now passes timing analysis, the minimum pulse width has 5.6 ns of slack. I can only assume that as the clock signal is now buffered by an LCELL, the minimum pulse width constraint isn't being applied to the internal node of the megafunction which had the minimum pulse width problem.

I'm posting this in case anyone else runs into the same problem, but from what I can gather, using the internal oscillator in the application code seems to be a very rare occurrence.