Honored Contributor
Honored ContributorIf you're doing gated clocks, TimeQuest will analyze all paths through the combinatorial logic and use the longest/shortest combinations to do the most restrictive analysis possible. To get the analysis you want, put keep attributes on the combinatorial places the clock comes out of(to keep the name through synthesis) and apply a generated clock constraint. Now you have a new clock name and can cut timing between combinations that aren't relevant.
For example, I worked on a design with a 4:1 clock mux, built out of three 2:1 muxes. The strange thing was that it used only 3 clocks, but one of them came into both first level 2:1 muxes(basically two different select values chose the same clock). So TQ would analyze setup by taking the longer path to the source register and the slower path to the destination register, and vice versa for hold analysis. This is all good, but we turned off the clocks when the mux switched, so these would never happen. So I put two generated clocks on each of the 2:1 outputs and cut timing between them all using a set_clock_groups constraint. (I don't know what you have, but that's the case where I've seen TQ do the longest and shortest analysis at the same time, so hopefully it's relevant.)
