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Altera_Forum's avatar
Altera_Forum
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15 years ago

Minimum Pulse Width violation

Hello, I have a design, where i am using a custom programmable delay line for shifting a clock. The delay line is implemented using and-or gates (as described in thread "Dynamic delay for LVDS ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

I think you can't avoid this. If I understand correctly, you want to change the delay "on the field" in order to adjust the timing "artificially". So TQ analysis makes no sense in this case.

If the input and output clocks of the delay line are related to different clock domains, you can simply set a false path between them to avoid the violation warning.