Forum Discussion
Farabi
Regular Contributor
9 months agoHello,
PLL design should be straight forward. Please make sure you recompile the design after you change devices and make sure the pin assignments are connect following the physical pin connection on your board.
Please make sure your clock oscillator is driving the correct IO standard signal into FPGA(please make sure the same IO standard is defined in IO pin planner as well).
regards,
Farabi