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Altera_Forum's avatar
Altera_Forum
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13 years ago

Mentor Precision & illegal altclockctrl inferring

Hi,

I'm having a problem with an implementation on Cyclone II EP2C8F256 technology. I am using 2 pins (F14 & F15) as clock inputs and I mux these clocks.

Usage of an altclkctrl is not permitted for these two pins, so I create the clock mux in logic. I know, it's not ideal... However the problem I am facing is Mentor Precision inferring automatically an altclkctrl block in this position => Quartus can't fit 


Error: Can't place clk_0 at location PIN F14 because it uses a Clock Control Block with dynamic clock select File: path_to_vqm/my.vqm
Error: Can't place clk_1 at location PIN F15 (LVDS45n) because it uses a Clock Control Block with dynamic clock select File: : path_to_vqm/my.vqm
Error: Can't fit design in device

Can anyone give me an idea how I can prevent Precision from inferring this illegal altclkctrl block?

In Precision .sdc I have defined the clock frequencies, pin location, so he should be aware of this...

Thanks!

===

P.S.

* I know these are not dedicated clock pins for the specified FPGA.

* Both clocks are 25 MHz

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi,

    unfortunately no reply until now.

    Can anyone direct me to some Mentor Precision forum or some other FPGA-related forum? The problem is becoming a show-stopper for me, and giving up Precision should not be the solution :(

    Thanks!
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Have you tried Quartus Synthesis?

    Its my understanding that Quartus gives the best results anyway (Synopsys told us that).
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Have you tried Quartus Synthesis?

    Its my understanding that Quartus gives the best results anyway (Synopsys told us that).

    --- Quote End ---

    Yes, I have tried Quartus and this problem does not occur.

    As for "best results" with Quartus, I doubt it... after all there is a reason why someone would pay some $$$ for a 3rd Party synthesis tool. The only thing I can be shure about Quartus synthesis is that it will know it's hardware better than a 3rd party tool. But intelligence in optimizing the netlist is inferior to Precision/Synplify

    Taking Precision out of the tool chain is not an option...
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Good luck

    The word I got from the Synopsys Sales Guys (I know its not mentor, but):

    "Xilinx are very open about letting 3rd parties write tools for them, and will admit that 3rd party tools are much better

    Altera are very closed to 3rd parties, and we cannot do better than their own Synthesis. I wouldnt bother buying Synplify if all you do is altera"

    So Im afraid you're stuck. If precision is the only option, I suggest you raise a bug report with them.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I have found a "solution": disabling the "fix gated clocks" option of Precision.

    However I still believe that even with this option set Precision shouldn't have broken the rule...

    Hope this post helps others.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    However I still believe that even with this option set Precision shouldn't have broken the rule...

    --- Quote End ---

    Possibly, but this is an issue you need to bring up with Mentor, not with Altera.