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Altera_Forum's avatar
Altera_Forum
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14 years ago

MEMORY issue

Hello,

I have a stupid question, I successfully compiled my project but I am not sure about the results:

--- Quote Start ---

Flow Status Successful - Mon Sep 26 12:17:31 2011

Quartus II Version 11.0 Build 157 04/27/2011 SJ Web Edition

Revision Name topmodule3

Top-level Entity Name topmodule3

Family Cyclone

Device EP1C20F400I7

Timing Models Final

Total logic elements 410 / 20,060 ( 2 % )

Total pins 80 / 301 ( 27 % )

Total virtual pins 0

Total memory bits 0 / 294,912 ( 0 % )

Total PLLs 0 / 2 ( 0 % )

--- Quote End ---

I dont know why my memory bits is still zero when I have this in my verilog topmodule:

(* ramstyle = "M144K" *) reg [FIXED_WIDTH-1:0] memX [0:MxN-1] ;

memX is a 50x50x 32 bits.

Also, My number of logic gates seems really small. I am implementing something that includes convolution, exponential etc. I would expect the number of logic gates to be more.

Sorry I am new at this.

Thank you

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Most likely you're logic is getting optimized due to an error in the code. Check your warnings and see if you have any clocks that are not connected or resets that are not connected, either can cause large blocks of logic to get optimized out due to simple type-o's.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thank you for the reply,

    What do you mean by clocks or reset not connected.

    Before,

    I had:

    Testbench

    Topmodule

    convolution

    and Mean_max module

    And all my simulations worked on modelsim

    I was told to

    Just add my topmodule and convolution and mean_max modules to quartus

    Make my topmodule the main entity

    I didnt change anything in the code or add anything tho.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Basically check your warning file from synthesis.. If you don't have a clock, you won't have any logic.

    It may not be clock, but I've seen type-o's kill an entire design, because an inadvertent character was put in a clock name.

    But it can be any wide arrange of issues. Just make sure you understand the warnings you are receiving. Also look at the post synthesis hierarchy and make sure it looks correct.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I just noticed this:

    --- Quote Start ---

    SEGMENT~4 Lost fanout

    SEGMENT~5 Lost fanout

    SEGMENT~6 Lost fanout

    SEGMENT~7 Lost fanout

    SEGMENT~8 Lost fanout

    Total Number of Removed Registers = 5

    --- Quote End ---

    I dont know if that makes sense to you.

    I was using different SEGMENTS so that i will be sure of what state I was in.