Memory data misplaced when initializing from .hex file

In simulation, there is no connection to the system, I`ve simulated just the bare vhdl file, generated by IP core. Respectivery, signals clock, address and q are going directly to the component.

In FPGA trial, I`ve tested this component inside following top-level design:

where CLK is 50MHz clock from external crystal oscillator, and LEDS[15..0] are GPIO outputs connected to 16 test LEDs on the board. Timing analysis suggest, that I can run CLK pin at 113MHz, so there is no clock issue. I`ve scanned my ROM by changing lpm_const_rom value, re-compiling and re-uploading it via JTAG. Still, I`m getting zero values for addresses 0x08 - 0x0F, while actual content of these are shifted to 0x10 - 0x18, exactly the way it was simulated. This gap is inserted after every 8-word blocks of data and always consists of 8 words of zeros.

So, obviously there is compile-time error and both Quartus and ModelSim read this file wrong due to some formatting incompatibility. The question is: how then the file should be formatted, in order to get rid of memory content displacement?