Forum Discussion
Altera_Forum
Honored Contributor
14 years agohi,
I go the same problem too. using the DE0-Nano board and follow the ALTPLL and Mux design in the baord user guide. when doing the Modelsim RTL simulation with lpm_ver and altera_mf_ver included, the C0 output just get hiZ. any advice? I convert the bdf to verilog format before using nativelink to trigger the modelsim-altera simulator. the C0 output just show hiZ. dont know why? I attached my project design file here, pls help.