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Altera_Forum
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10 years ago

Maximum Operating Frequency

Hi everybody, I designed a sample architecture in Quartus 10.1 by using EP4CE22F17C6. I used a bit generator and parallel mux blocks and run all architectures. I connect output of the bit gener...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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but thats it - the path is not always fixed.

When it does the fit, the logic can get put in different places, so the routing delays can vary from build to build - hence the variability.

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Tricky and Alex96 thank you for your comments. I now understand it. I obtained some examples in chip planer and atteched at this message.