MAX10 set_false_path failure

Hi, apologies for late reply - sidetracked on another project. I tried your suggestion to add a false_path constraint into the sdc file: set_false_path -from [get_clocks *] -to [get_registers {CDC_2FF:inst14|ff1}]

The -to ... ff1, is the first register in the CDC (clock domain crossing) module. The sdc false_path wizard created the -from [get_clocks *] even tho I had selected the clock signal name for the source clock, that originates from the pll. (the destination clock also originates from the same pll, at a higher frequency than source).

There were no warnings/errors re. failed constraint during compile. However, the false_path didn't have any effect; same timing error. Timing Analyzer - report false_path returned "nothing to report" which seems to indicate the above constraint didn't capture the path correctly? I am not understanding what it takes to get a false path to work with this part family. Maybe you can point me to a specific real-world example of how to apply a false path constraint to a CDC module?

Thank you.