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NM8
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7 years ago
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MAX10 FPGA Pin Assignments for LVDS signals input and outputs

Hi, We are using MAX10 FPGA(10M40SCE144C8G) with our board. We want to connect multiple input and output LVDS signals to one of the banks of this FPGA. To use the true LVDS (TX or RX) should we use...
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NM8
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7 years ago

Hi Abe,

"Since you've assigned Bank2 as 3.3V LVCMOS and LVDS IO Standard, the IO Buffers in the device for Bank2 are configured as LVDS IO buffers. These can accept single-ended signals as inputs but cannot output single-ended signals."

  • Does it mean that I do not have to give a 2.5V supply for the LVDS signals (i.e. to VCCIO).

Am I correct to understand that I can implement any LVDS signals in 3.3V bank but with limitation as no 3.3V single ended output signals are allowed in that bank.

If above statement is right, what would be the common mode voltage of the LVDS signals(from 3.3V bank voltage)?

As per the datasheet, the LVDS signals are defined only with VCCIO=2.5V in the table.

Thanks & Regards,

Nanjunda M

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NM8
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7 years ago

Hi

Does anyone tell me whether my above statement is correct or wrong?

Thanks & Regards,

Nanjunda M