MAX10 FPGA Pin Assignments for LVDS signals input and outputs

Hi,

The issue is due to the limited number of pins for each bank in the E144 package of Max10 device you're using, each bank can be assigned only a single IO Voltage standard as well as IO Standard.

Since you've assigned Bank2 as 3.3V LVCMOS and LVDS IO Standard, the IO Buffers in the device for Bank2 are configured as LVDS IO buffers. These can accept single-ended signals as inputs but cannot output single-ended signals.

The error message says whats wrong:

Error (169027): Pin Extr1 is incompatible with I/O bank 2. Pin uses I/O standard 3.3-V LVCMOS, which has a VCCIO requirement incompatible with that bank's VCCIO setting or other pins that use I/O standard LVDS.

If you look at your pin-outs, the other single-ended signal in the same bank (Bank2) is an input, along with two LVDS input clocks. So this is okay. But when you assign output signal which is single-ended to the same LVDS bank, the IO buffer cannot drive the same as single-ended.

What you need to do is to assign any single-ended output signals in your design to other banks that are configured as 3.3V LVCMOS and non-differential. Assigning the same EXTR1 output to IO Bank 1B just above Bank2 solves the issue and the compile goes through.

These are the limitations when working with different IO voltages and standards on FPGA devices that you have to keep in mind when assigning pins. Please read the IO documentation before making any pin assignments.