Max10 ADC simulation in QuestaSim fails to simulate output

I'm trying to simulate the Max10 ADC in QuestaSim 2021.3. The ADC Core ready signal (modular_adc_0_command_ready) never goes high. I suspect that the following warning may be related to this behaviour:

Warning: (vsim-PLI-3691) Expected a system task, not a system function '<protected>'.
#    Time: 0 ps  Iteration: 0  Protected: /adc_controller_tb/adc_controller/modular_adc_0/control_internal/adc_inst/adcblock_instance/primitive_instance/inst/<protected>/<protected>/<protected> File: J:/Programme/intelFPGA_lite/18.1/quartus/eda/sim_lib/mentor/fiftyfivenm_atoms_ncrypt.v Line: 38

To me, it looks like QuestaSim can not read the encrytped IP file fiftyfivenm_atoms_ncrypt.v. I did compile the altera libraries for both verilog and vhdl using Quartus Prime 20.1.0 lite and used the 'Run Simulation Tool> RTL Simulation' command of quartus to set up the simulation in QuestaSim.

I attach the log files of the library compilation, as I have noticed that for the file fiftyfivenm_atoms_ncrypt.v, no top level modules are listed. Is this the expected behaviour during library compilation?

Any help is appreciated.