--- Quote Start ---
Created a separate COMPONENT triggered by the 100 MHz clock to create my 12_5MHz clock and instanciated in "Sawtoothx" entity. It seems to work better. I will try an "enable" signal if I see some other issues.
--- Quote End ---
A component doesn't change anything. At least SAWTOOTH_CLOCK must be registered. (It might be that the combinational expression for SAWTOOTH_CLOCK maps to a single FF output. In this case, it would be glitch-free without being explicitely registered)
You have several domain crossing signals with i_clock as launching and SAWTOOTH_CLOCK as latching clock which likely causes timing violations, e.g. current_state.
I guess there's no substantial reason for this clock topology. Using SAWTOOTH_CLOCK respectively a new signal that is active for one i_clock cycle as a clock enable is however the straightforward way to get rid of domain crossing problems.
Or don't register any internal signals under i_clock control.
Honored Contributor
