Honored Contributorhi
i have a problem with my altera max device. it does not enter into the process despite the constantly updated clock: q<=q_temp; ff: process(clk) begin IF (clk'event) AND (clk='1') and (en='1') THEN -- Positive Edge q_temp <= d; elsif (en='0') then q_temp<=q_temp; END IF; if (reset='1') then q_temp <='0'; end if; end process; thanks
Honored ContributorIt seems to me, that you actually meaned to code the below process:
ff: process(clk)
IF (reset='1') THEN
q_temp <='0';
ELSIF (clk'event) AND (clk='1') THEN -- Positive Edge
IF en='1' THEN
q_temp <= d;
ELSE
q_temp<=q_temp;
END IF;
END IF;
end process;but the code inside the process isn't executed.
The device doesn't come in the process. i test the code that you have sent me!!! soonHonored ContributorI assumed, that Quartus would possibly misunderstand the asynchronous (outside clock edge) hold condition
elsif (en='0') then q_temp<=q_temp; But I verified, that both variants exactly infer a DFFE primitive in mapped design. So if everything seems wrong, it's most likely a simulation problem. The code behaves as a D-Flip-Flop with clock enable, as it should.Honored Contributori have built the project and programmed the device but doesn't work!
could be a hardware problem on the clock? sure that the CPLD covering the process statement? I inserted a quartz gclk1 at 8 MHz (pin 43)! without capacitors thank'sHonored ContributorHonored Contributorthe clock works! I made a program to test it, even if it behaves erratically. Oscillates only if I get close! Where can I find a pattern for the clock?
Honored ContributorI made an asynchronous circuit with a process statement!
the process is update by a pin connected to an external switch. Not work ther is another problem. does not recognize initial allocations. For example: signal a:std_logic:='0'; however i renew my request: Where can I find a pattern for the clock?
