Contributor
ContributorNow Flash controller test:
reenable has lost csr interface.
Qsys on reenable report clock and reset error, but they where on place:
double click on both clock and reset remove error.
Data has no address map, double click on data connection restore.
Save (forever twice) generate, then Quartus compile design to end. (not initialized flash.)
reopen qsys, delete Flash IP, select again from IP it is mapped where it was previous, again erase don't work. CSR reappear.
Flash is set as not initialized
Flow Status Successful - Sat May 25 00:11:17 2019
Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Revision Name Top
Top-level Entity Name top
Family MAX 10
Device 10M08SCE144C8G
Timing Models Final
Total logic elements 5,683 / 8,064 ( 70 % )
Total registers 2210
Total pins 95 / 101 ( 94 % )
Total virtual pins 0
Total memory bits 33,476 / 387,072 ( 9 % )
Embedded Multiplier 9-bit elements 0 / 48 ( 0 % )
Total PLLs 1 / 1 ( 100 % )
UFM blocks 1 / 1 ( 100 % )
ADC blocks 0
Reload Qsys, check initialize memory, point to bios for embedded processor, save and generate QSYS.
Quartus compile sa with uninitialized memory.
Browsing .pof and .sof with an HEX viewer no trace of bios is seen on files.
Try with convert programming files...
MAX 10 can be an Heaven to embedded SOC, turn on Hell by software and lack of documentation....
Edit UPDATE:
modified configuration of flash to initialized, added .hex bios files, everything proceeded fine.
Flash content where is stored on .pof? or .sof? I don't see bios ascii messages, nor I see code, just a long FF sequence and some spot of noise, can be cfm
