Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

matrix multiplication using verilog

I have coded a matrix multiplication. matrix size is 4 by 4 and the data size is 1 bit. It shows some structure in RTL view but nothing is seen is technology map viewer and it shows 0 LEs are used. Please help.....

//matrix multiplication:

module matmul(clk,a,b,c);

input clk,a,b;

output reg c;

reg sum;

reg ra[3:0][3:0];

reg rb[3:0][3:0];

reg rc[3:0][3:0];

integer i1,i2,i3,j1,j2,j3,k;

always@(posedge clk)

for(i1=0;i1<=3;i1=i1+1)

begin

for(j1=0;j1<=3;j1=j1+1)

begin

ra[i1][j1]=a;

rb[i1][j1]=b;

end

end

always@(posedge clk)

for(i2=0;i2<=3;i2=i2+1)

begin

for(j2=0;j2<=3;j2=j2+1)

begin

sum=1'b0;

for(k=0;k<=3;k=k+1)

begin

sum=sum^ra[i2][k]*rb[k][j2];

end

rc[i2][j2]=sum;

end

end

always@(posedge clk)

for(i3=0;i3<=3;i3=i3+1)

for(j3=0;j3<=3;j3=j3+1)

c=rc[i3][j3];

endmodule

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Which device are you using? Maths functions are optimized mostly using DSP/embedded multiplier where applicable. But it would be rare to have 0 LEs used at all.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I'm a bit rusty, but won't 'ra' always be a 4x4 matrix of all ones or all zeros depending on the state of 'a' at the rising edge of clk? And likewise for 'rb'? So the output will always be a 4x4 matrix of zeros since in all cases 'sum' resolves to 0 since the matrix length is even?

    ((((0 xor 0*0) xor 0*0) xor 0*0) xor 0*0)=0

    ((((0 xor 1*0) xor 1*0) xor 1*0) xor 1*0)=0

    ((((0 xor 0*1) xor 0*1) xor 0*1) xor 0*1)=0

    ((((0 xor 1*1) xor 1*1) xor 1*1) xor 1*1)=0

    Maybe try an odd matrix dimension and see if you get a different result.