Forum Discussion
New ContributorMaths Error
Why not do a fully synchronous design with all the registers clocked on posedge clk ?
Create an enable signal for the data processing block and include all the logic inside that block within it:
always @ (posedge clk) begin
if (enable_enc) begin
... do stuff ...
end
end
Regular ContributorWhy not do a fully synchronous design with all the registers clocked on posedge clk ?
Create an enable signal for the data processing block and include all the logic inside that block within it:
always @ (posedge clk) begin
if (enable_enc) begin
... do stuff ...
end
end
New ContributorTwo questions.
Why would that work when my solution does not?
What is best practice for implementing enable_enc?
- ak6dn
Using a single synchronous clock with optional register enable(s) is simpler for Quartus to meet timing than deriving a bunch of signals that will be used as clocks. FPGAs only have a limited number of low skew, high drive clock layout resources.
As to implementing the enable signal, that is just some simple logic driving a register to create a one clock width pulse at the posedge clk when you want the logic to trigger. No special techniques needed.
