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DBarn22's avatar
DBarn22
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Maths Error

I have a block that is occasionally giving an error. I'm fairly sure it is due to timing, but I do not understand the problem. The following are relevant snippets. reg enc_reg; reg [31:0] e...
  • ak6dn's avatar
    ak6dn
    5 years ago

    Why not do a fully synchronous design with all the registers clocked on posedge clk ?

    Create an enable signal for the data processing block and include all the logic inside that block within it:

    always @ (posedge clk) begin
    if (enable_enc) begin
    ... do stuff ...
    end
    end

DBarn22's avatar
DBarn22
Icon for New Contributor rankNew Contributor
5 years ago

I tried a different solution...

always @ (negedge enc_reg) begin
	enc_real_fast_time_prev <= enc_real_fast_time;
	enc_real_fast_time <= fast_now;
end

wire [31:0] enc_pulse_period;
assign enc_pulse_period = (enc_real_fast_time - enc_real_fast_time_prev) / divider;

(Currently not quite the same functionality as it divides over one rather than two periods, but that is just detail).

What this has shown is that the division takes many clock cycles to perform. Therein lies my problem.


This may be a sufficient solution for what I need. I would still be interested to know if it is possible to do what I was initially trying to do.

ak6dn's avatar
ak6dn
Icon for Regular Contributor rankRegular Contributor
5 years ago

Why not do a fully synchronous design with all the registers clocked on posedge clk ?

Create an enable signal for the data processing block and include all the logic inside that block within it:

always @ (posedge clk) begin
if (enable_enc) begin
... do stuff ...
end
end

  • DBarn22's avatar
    DBarn22
    Icon for New Contributor rankNew Contributor
    5 years ago

    Two questions.

    Why would that work when my solution does not?

    What is best practice for implementing enable_enc?

    • ak6dn's avatar
      ak6dn
      Icon for Regular Contributor rankRegular Contributor
      5 years ago

      Using a single synchronous clock with optional register enable(s) is simpler for Quartus to meet timing than deriving a bunch of signals that will be used as clocks. FPGAs only have a limited number of low skew, high drive clock layout resources.

      As to implementing the enable signal, that is just some simple logic driving a register to create a one clock width pulse at the posedge clk when you want the logic to trigger. No special techniques needed.