Math calculations in VHDL

I modified the code so it compiles now but I still get a quotient and a remain and not the whole result. Besides, if my input is std_logic_vector why convert it to ufixed and then back to std_logic_vector?

Library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.fixed_float_types.all;

use ieee.fixed_pkg.all;

entity PreNICOMFunction_fixed is

port (

clock : in std_logic;

reset : in std_logic;

I : in std_logic_vector (31 downto 0);

Q : in std_logic_vector (31 downto 0);

V0 : in std_logic_vector (31 downto 0) --;

-- temp_res : out ufixed (31 downto -32)

);

end PreNICOMFunction_fixed;

architecture rtl of PreNICOMFunction_fixed is

component lpm_divider1 IS --32 clocks latency

PORT (

aclr : IN STD_LOGIC ;

clock : IN STD_LOGIC ;

denom : IN STD_LOGIC_VECTOR (63 DOWNTO 0);

numer : IN STD_LOGIC_VECTOR (63 DOWNTO 0);

quotient : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);

remain : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)

);

END component lpm_divider1;

type fsm_type1 is (s0, s1, s2, s3, s4);

signal fsm1 : fsm_type1 := s0;

signal QdivI : std_logic_vector (63 downto 0) := (others => '0');

signal QdivI_remain : std_logic_vector (63 downto 0) := (others => '0');

signal I_ff : std_logic_vector (31 downto 0) := (others => '0');

signal Q_ff : std_logic_vector (31 downto 0) := (others => '0');

signal I_fp : ufixed (31 downto -32) := (others => '0');

signal Q_fp : ufixed (31 downto -32) := (others => '0');

signal div_res : ufixed (31 downto -32) := (others => '0');

signal cntr1 : ufixed (4 downto 0) := (others => '0');

constant div_latency : ufixed (4 downto 0) := "11111";

begin

divider : component lpm_divider1

port map (

aclr => '0',

clock => clock,

denom => to_slv(I_fp),

numer => to_slv(Q_fp),

quotient => QdivI,

remain => QdivI_remain

);

main : process (clock)

begin

if (rising_edge(clock)) then

I_ff <= I;

Q_ff <= Q;

case fsm1 is

when s0 => if ((I_ff /= I) or (Q_ff /= Q)) then --New data availabe

I_fp <= to_ufixed(unsigned(I),31,-32);

Q_fp <= to_ufixed(unsigned(Q),31,-32);

fsm1 <= s1;

end if;

when s1 => if (cntr1 < div_latency) then --Wait for the division operation to complete (Q/I)

cntr1 <= resize(cntr1 + 1, cntr1'high, cntr1'low);

else

cntr1 <= (others => '0');

fsm1 <= s0;

end if;

when others => fsm1 <= s0;

end case;

end if;

end process main;

end rtl;