Math calculations in VHDL

Yes, you will get a fraction. But if they start out as 32 bit, you will need a lot more bits to store the result. But making it a 32.32 sfixed is rather easy (remember integers are signed. For unsigned, you can only have a max of 31 bit integers). Do you really mean integers as in the VHDL type integer, or just a number that arrives via a 32 bit bus?

signal my_number : sfixed(31 downto -32);

my_number <= to_sfixed(input, 31, -32);

And this is free in terms of synthesis because you're really just appending a load of zeros to it. Then you can convert this to a std_logic_vector (with the to_slv function) so you can connect it into the lpm divide. No, you should not use the "/" function unless you can get away with a pipeline length of 1 (until altera sort out their register placement inside infered dividers properly!)

you shouldnt do + with std_logic_vectors, you should keep them in ufixed or sfixed type when you do this.

I think at this point you need to post some code to show us what you're actually trying to do.