Marble line

You should write a testbench - the testbench will help you debug it without having to go to hardware (it is much harder to debug on hardware).

You need to make your process sensitive to clock, not red/blueMarble.

Be aware that for loops will unroll into the worst case hardware. So for your code, it is a long chain of 2:1 muxes.

Other points to note:

Using integers makes the values 32 bit. You probably want to limit the range to limit the bit-width (the synthesisor may trim this for you).

You can use an integer array as an output, but I wouldnt do it for the top level, as you would need to map all the bits to pins on the chip. In VHDL you have no direct access to the bits in an integer (they dont exist in VHDL, the synthesisor maps them for you) so its best to go with some std_logic array type (usually std_logic_vector or signed or unsigned).