Honored Contributor
Honored ContributorOkay, now I could compile it!
I didn't get the output I was expecting though. Here is the code:
library IEEE;
use IEEE.std_logic_1164.all;
Entity Central is
generic (N: integer := 9);
port(
clock, redMarble, blueMarble: in std_logic;
outLine: out std_logic_vector(N downto 0)
);
end Central;
architecture archC of Central is
type Vector is array (N downto 0) of integer;
signal marbleLine : Vector;
begin
process(redMarble, blueMarble) is
variable alreadyFoundFirstZero: std_logic;
begin
alreadyFoundFirstZero := '0';
if(rising_edge(clock)) then
if(redMarble = '1' and blueMarble = '0') then
-- Here I will look for the first empty space, or 0, in the marbleLine
for i in 0 to N loop
if(alreadyFoundFirstZero = '0') then
if(marbleLine(i) = 0) then
marbleLine(i) <= 1;
alreadyFoundFirstZero := '1';
end if;
end if;
end loop;
elsif(redMarble = '0' and blueMarble = '1')then
for i in 0 to N loop
if(alreadyFoundFirstZero = '0') then
if(marbleLine(i) = 0) then
marbleLine(i) <= 2;
alreadyFoundFirstZero := '1';
end if;
end if;
end loop;
end if;
end if;
end process;
-- Testing Output
process(marbleLine) is
begin
for i in 0 to N loop
if (marbleLine(i)= 1) then
outLine(i) <= '1';
end if;
if (marbleLine(i)= 2) then
outLine(i) <= '0';
end if;
end loop;
end process;
end archC;
