Mapping inout to inout

You should avoid doing this. The inout is only for IO and a direction should always be given. You could create a short circuit when you drive one high and another low.

[edit]sorry missed the part about the separate board, you do need to use a bidirectional driver if you want the io to function both as in and out in the same design[/edit]

I'm sorry, why not? Perhaps I wasn't clear enough, but the point is not to have multiple drivers or bidir functionality, but to push the location in the design where the input or output direction is chosen. This might sound strange, but please consider the following use case:

The top-level FPGA design and pin mapping is matching the PCB net names, which use GPIO[] as a generic inout port on this eval kit. This port is connected to a pin-header and to a daughter board. On this daughter board the schematics name the signals coming from the FPGA is named DSP[]. This specific board makes use of DSP(0) as mclk output, DSP(1) as sdout output, DSP(2) as sdin input. It is the latter pins that actually determines the directions of the function.

From a design point of view, I know that I want mclk as input. And the design where mclk is being used, expects this as input. But the generic connection HW layers/PCB does not care if its an input or output. I really have to study the details and layers of the schematics to understand that this corresponds to the FPGA pin GPIO(0) and that it is an input. IMHO I think it would be great if the verilog design could reflect the actual HW hierarchy. By configuring the GPIOs as generic inout (as the eval kit GHRD does) and make the functional submodule that actually use the signal determine the direction of the port. I have already made manual mapping mistakes due to mixups where I was cross eyed when following the schematics across design layers.

Something like this:

modules:  top <---> dspboard_pinmap             ---> mainfn
inout GPIO(0) <---> inout GPIO(0), inout DSP(0) ---> input mclk

Hence, GPIO(0), DSP(0) and mclk are indeed the same "wire". And the pin is an input. It's easier to validate layer by layer, module by module individually

sveinse -

You can definitely do what you want to do, and it sounds like you're well on your way to figuring out a way to do it. For each inout pin you'll have to handle the input and output signals separately internally, as well as an enable for the output buffer. You could then have sub-modules that drive the select lines that control the direction of each pin based on parameter inside the module. It's all very doable.