MAP is taking a day to complete

Hi,

During an FPGA image generation, the build takes an entire day in MAP phase and we are unable track in which phase it's getting stuck or taking more time. Once MAP is done, it takes another 4 hours to generate the image. Following is a transcript of MAP report :

Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:29:37

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Info (21057): Implemented 449846 device resources after synthesis - the final resource count might be different

Info (21058): Implemented 465 input pins

Info (21059): Implemented 464 output pins

Info (21060): Implemented 7 bidirectional pins

Info (21061): Implemented 439628 logic cells

Info (21064): Implemented 8863 RAM segments

Info (21065): Implemented 2 PLLs

Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 2692 warnings

Info: Peak virtual memory: 12386 megabytes

Info: Processing ended: Wed Oct 22 06:15:43 2014

Info: Elapsed time: 23:57:34

Info: Total CPU time (on all processors): 23:54:46

FPGA Device Used : EP4SE820F43C3 (Stratix IV)

Tool : Quartus II 64-Bit Version 14.0.0

Thanks & Regards,

Kiran