manual placement of components

hi,

any reference document that describes this task?

thank you,

randeel.

LogicLock regions is another option:

Best Practices for Incremental Compilation Partitions and Floorplan Assignments

http://www.altera.com/literature/hb/qts/qts_qii51017.pdf

found it,

set_location_assignment FF_X16_Y1_N31 -to "component_name"

it is written to the qsf file.

type of thing can be done

http://www.altera.com/education/training/courses/odsw1155

describes how to use chip planner to do Assignments

thank you,

randeel.

Is there a chance to synthesize a script which generates placement contraints automatically from given demands?

I have the task to create a certain structure which has to be organized in a kind a matrix in order to obtain the most possible clean routing delay characteristics between modules.:rolleyes:

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Is there a chance to synthesize a script which generates placement contraints automatically from given demands?

I have the task to create a certain structure which has to be organized in a kind a matrix in order to obtain the most possible clean routing delay characteristics between modules.:rolleyes:

--- Quote End ---

Hi fpgaengineerfrankfurt,

HAve you found a way which generates placement contraints automatically from given demands? I have the same issue. I need to fix the placement of modules in fpga

Thanks