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Your frame is 6400 samples each 14 bits. That needs 89600 bits (87.5K). You can do that in many FPGAs and it suits large rams. You may need to use either two such rams or one fifo.
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I am using Cyclone IVE FPGA which has 2 MB SRAM. I am planning to use this SRAM in following way (with right pin assignment for SRAM) for this purpose::
library ieee;
use ieee.std_logic_1164.all;
entity single_port_ram is
port
(
data : in std_logic_vector(13 downto 0);
addr : in natural range 0 to 6399;
we : in std_logic := '1';
clk : in std_logic;
q : out std_logic_vector(13 downto 0)
);
end entity;
architecture rtl of single_port_ram is
type memory_t is array(0 to 6399) of std_logic_vector(13 downto 0);
signal ram : memory_t;
signal addr_reg : natural range 0 to 6399;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(we = '1') then
ram(addr) <= data;
end if;
addr_reg <= addr;
end if;
end process;
q <= ram(addr_reg);
end rtl;
Does it work for this purpose or not??
One more thing, how can I extract/access these 6400 samples of data on PC every time may be in some text file format?
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