Managing input on the FPGA board

Your frame is 6400 samples each 14 bits. That needs 89600 bits (87.5K). You can do that in many FPGAs and it suits large rams. You may need to use either two such rams or one fifo.

Two rams in case one may overflow/underflow so one reads ADC while the other is read to PC then swap the order. Your main task is to do the swap logic.

Or use fifo controlling rate so that PC catches up in time. Your main task here is to match the read/write speeds.